1. Technical Field
The present invention relates to digital computers and more particularly to a system for timing the signals on the I-O bus of a personal computer.
2. Prior Art
Many of the personal computers which are presently available utilize an 80286 microprocessor. Personal computers which utilize an 80286 microprocessor generally have an I-O bus which is controlled by an 82-288 bus controller chip. Other presently available personal computers utilize an 80386 microprocessor. Personal computers which utilize an 80386 microprocessor generally have discrete logic associated therewith which controls the associated I-O bus.
In existing computers which utilize 80286 or 80386 microprocesors the same clock signal drives both the microprocessor and the bus controller. If for example a personal computer utilizes an 80286 microprocessor which is driven at six megahertz the associated 82-288 bus controller is also driven at six megahertz. Some existing personal computers can be switched between two clock frequencies; However, in such computers when the clock driving the microprocessor is switched, the clock driving the bus controller is also switched.
The bus controllers used in personal computers generate a series of standard signals. The signals on a PC bus are, for example, described in an article entitled "Three Bus Interface Designs for the PC", which appeared in BYTE The Small Systems Journal, Volume 12, Number 12, pages 225 to 245, 1987. The signals present in what is known as the AT Bus are described in many publications including a publication entitled the "IBM AT Technical Reference Manual" which is commercially available from IBM.
Among the signals on both the PC and the AT bus, are signals termed the COMMAND signal and the ADDRESS LATCH ENABLE (or ALE) signal. The COMMAND signal occurs at a specified time after the ALE signal. The time between the ALE signal and the COMMAND signal is termed the COMMAND DELAY. In the PC bus the COMMAND DELAY has a fixed value equal to ONE. In the AT bus the COMMAND delay has a value of "one" when an eight bit memory I-O bus is being used, and a value of "zero" when a sixteen bit memory bus is being used.
In both the PC bus and the AT bus, a COMMAND signal is terminated after a period of time known as the WAIT STATE DELAY. In the PC bus the WAIT STATE DELAY has one fixed value. In the AT bus the WAIT STATE DELAY has a value of "four" for eight bit cycles and a value of "one" for sixteen bit cycles.
The bus systems for present PC and AT systems are relatively inflexible because the COMMAND DELAY and the WAIT STATE DELAY have fixed values that are dictated by the machine designers. Furthermore the microprocessor clock, the bus clock, the COMMAND DELAY, and the WAIT STATE DELAY are all tied to the frequency of a single clock. This lack of flexibility in presently available Personal Computers creates problems with various devices such as with slower operating device. In general a system clock speed must be selected which accommodates the slowest device.
An article entitled "Three Bus Interface Designs for the PC", which was published in BYTE The Small Systems Journal, Volume 12, Number 12, 1987, discusses bus timing and it makes the observation that cards designed to work on a personal computer with one clock speed may not work on a processor with a different clock speed. This article suggests that the solution is to use high speed chips whenever possible. Such a solution may be overly expensive to implement.